High performance integrated circuit designs generally require multiple optimization steps to push performance and minimize leakage power resulting in large runtime requirements. For example, leakage recovery can take 30% of the total circuit optimization runtime. The necessity for such optimization continues to increase, along with its computational cost, as circuit designs become bigger and more complex. Historically, turn-around-times for circuit optimization and layout tend to be between 1-3 days, so if leakage optimization consumes 30% of computation time, this can imply up to 24 hours of runtime for leakage optimization.